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ComponentType Structure for Front-end Chip

Notice

Page generated: 2023-06-01

See source code here

For updates/fixes contact: wraightATcern.ch

Tables generated from PDB componentType data-strucutre

Types

name code existing
RD53A RD53A True
ITkpix_V1 ITKPIX_V1 True
ITkpix_V2 ITKPIX_V2 True
ITkpix_V1.1 ITKPIX_V11 True
Tutorial FE chip TUTORIAL_CHIP True

Properties

name code description required
Wafer serial number WAFERSN wafer name False

Flags

name code
Bad at bumping BAD_AT_BUMPING
Bad at dicing/picking BAD_AT_DICING
Bad in flipchip BAD_AT_FLIPCHIP
Bad at handling BAD_AT_HANDLING
Bad at glass substrate removal BAD_AT_SUBSTRATE_REMOVAL
Bad at chip testing on wafer BAD_AT_TESTINGONWAFER
Yellow at chip testing on wafer YELLOW_AT_TESTINGONWAFER
Wrong iref trimming routine used during wafer probing do not use trim bits stored in db WRONG_IREF_TRIM_FROM_WAFER_TESTING
Wrong efuse number WRONG_EFUSE_NUMBER
engineering run ENGINEERING_RUN

Stages

Table

name code order alternative initial final
Testing on wafer TESTONWAFER 0 False True False
Hybridisation HYBRIDISATION 1 False False False
Not to be used for detector UNUSABLE 2 True False False
Bare module assembly BAREMODULEASSEMBLY 3 False False False
Reception at ITk institute BAREMODULERECEPTION 4 False False False
Bare module to module PCB assembly MODULE/ASSEMBLY 5 False False False
Wire Bonding MODULE/WIREBONDING 6 False False False
Initial Warm MODULE/INITIAL_WARM 7 False False False
Initial Cold MODULE/INITIAL_COLD 8 False False False
Parylene Masking MODULE/PARYLENE_MASKING 9 False False False
Parylene Coating MODULE/PARYLENE_COATING 10 False False False
Parylene Unmasking MODULE/PARYLENE_UNMASKING 11 False False False
Post-Parylene Warm MODULE/POST_PARYLENE_WARM 12 False False False
Post-Parylene Cold MODULE/POST_PARYLENE_COLD 13 False False False
Wirebond Protection (alt) MODULE/WIREBOND_PROTECTION 14 False False False
Thermal Cycles MODULE/THERMAL_CYCLES 15 False False False
Long Term Stability Test MODULE/LONG_TERM_STABILITY_TEST 16 False False False
Final Warm MODULE/FINAL_WARM 17 False False False
Final Cold MODULE/FINAL_COLD 18 False False False
Modules failed test, needs investigation MODULE/UNHAPPY 19 True False False
Module Complete MODULE/COMPLETE 20 False False False
Test after Loaded local support assembly TEST_AFTER_LOADED_LOCAL_SUPPORT_ASSEMBLY 21 False False True

Mermaid Diagram

flowchart LR subgraph Production Stages subgraph "Testing on wafer" a1["code: TESTONWAFER"] a2["tests: Electrical FE chip tests "] end subgraph "Hybridisation " b1["code: HYBRIDISATION"] b2["tests: "] end subgraph "Not to be used for detector (alternative)" c1["code: UNUSABLE"] c2["tests: "] end subgraph "Bare module assembly" d1["code: BAREMODULEASSEMBLY"] d2["tests: "] end subgraph "Reception at ITk institute" e1["code: BAREMODULERECEPTION"] e2["tests: Minimal Health Test Analog Readback "] end subgraph "Bare module to module PCB assembly" f1["code: MODULE/ASSEMBLY"] f2["tests: "] end subgraph "Wire Bonding" g1["code: MODULE/WIREBONDING"] g2["tests: "] end subgraph "Initial Warm" h1["code: MODULE/INITIAL_WARM"] h2["tests: ADC Calibration Analog Readback SLDO VCAL Calibration Low Power Mode Overvoltage Protection Undershunt Protection Data Transmission Injection Capacitance Minimal Health Test Tuning Pixel Failure Analysis "] end subgraph "Initial Cold" i1["code: MODULE/INITIAL_COLD"] i2["tests: ADC Calibration Analog Readback SLDO VCAL Calibration Injection Capacitance Tuning Minimal Health Test Pixel Failure Analysis Low Power Mode Overvoltage Protection Undershunt Protection Data Transmission "] end subgraph "Parylene Masking" j1["code: MODULE/PARYLENE_MASKING"] j2["tests: "] end subgraph "Parylene Coating" k1["code: MODULE/PARYLENE_COATING"] k2["tests: "] end subgraph "Parylene Unmasking" l1["code: MODULE/PARYLENE_UNMASKING"] l2["tests: "] end subgraph "Post-Parylene Warm" m1["code: MODULE/POST_PARYLENE_WARM"] m2["tests: ADC Calibration Analog Readback Overvoltage Protection Undershunt Protection SLDO VCAL Calibration Data Transmission Injection Capacitance Minimal Health Test Tuning Pixel Failure Analysis Low Power Mode "] end subgraph "Post-Parylene Cold" n1["code: MODULE/POST_PARYLENE_COLD"] n2["tests: ADC Calibration Analog Readback VCAL Calibration Low Power Mode Data Transmission Overvoltage Protection Undershunt Protection SLDO Minimal Health Test Tuning Pixel Failure Analysis Injection Capacitance "] end subgraph "Wirebond Protection (alt)" o1["code: MODULE/WIREBOND_PROTECTION"] o2["tests: Minimal Health Test Pixel Failure Analysis "] end subgraph "Thermal Cycles" p1["code: MODULE/THERMAL_CYCLES"] p2["tests: Minimal Health Test Pixel Failure Analysis "] end subgraph "Long Term Stability Test" q1["code: MODULE/LONG_TERM_STABILITY_TEST"] q2["tests: Minimal Health Test Pixel Failure Analysis "] end subgraph "Final Warm" r1["code: MODULE/FINAL_WARM"] r2["tests: ADC Calibration Analog Readback SLDO VCAL Calibration Undershunt Protection Overvoltage Protection Injection Capacitance Data Transmission Injection Capacitance Minimal Health Test Pixel Failure Analysis Tuning "] end subgraph "Final Cold" s1["code: MODULE/FINAL_COLD"] s2["tests: ADC Calibration Analog Readback SLDO VCAL Calibration Injection Capacitance Low Power Mode Overvoltage Protection Undershunt Protection Tuning Minimal Health Test Pixel Failure Analysis Data Transmission "] end subgraph "Modules failed test, needs investigation (alternative)" t1["code: MODULE/UNHAPPY"] t2["tests: "] end subgraph "Module Complete" u1["code: MODULE/COMPLETE"] u2["tests: "] end end subgraph Final Stages subgraph "Test after Loaded local support assembly" v1["code: TEST_AFTER_LOADED_LOCAL_SUPPORT_ASSEMBLY"] v2["tests: OB:Loaded local support QC electrical connectivity OB:Loaded local support QC electrical performance OB:Loaded local support reception at the integration site OB:Loaded local support QC electrical low power "] end end

Relatives

Parents

type: *

name code
Front-end Chips Wafer FE_WAFER
Bare Module BARE_MODULE
Bare Module BARE_MODULE
Bare Module BARE_MODULE
Bare Module BARE_MODULE
Bare Module BARE_MODULE
Bare Module BARE_MODULE

type: RD53A

name code
Front-end Chips Wafer FE_WAFER

type: ITKPIX_V11

name code
Front-end Chips Wafer FE_WAFER

type: ITKPIX_V1

name code
Front-end Chips Wafer FE_WAFER

type: TUTORIAL_CHIP

name code
Bare Module BARE_MODULE
Front-end Chips Wafer FE_WAFER

Children