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ComponentType Structure for HCC Chip

Notice

Page generated: 2023-06-01

See source code here

For updates/fixes contact: wraightATcern.ch

Tables generated from PDB componentType data-strucutre

Types

name code existing
HCC130 HCC130 True
HCCStarv0 HCCSTAR True
HCCStarv1 HCCSTARV1 True

Properties

name code description required
eFuse ID Hex EFUSE_HEX eFuse ID (hex) True
eFuse ID EFUSE eFuse ID (integer) False
Chip Quality QUALITY Quality flag for the chip, with 0=failed, 1=passed, and 2+ being various levels of acceptable False
Probe Location PROBE_LOCATION Location where probing occured False
Number of Probe Attempts N_PROBE_ATTEMPTS Number of times this chip was probed False
Final Probe Timestamp FINAL_PROBE_TIMESTAMP Timestamp for the final probing, from which data is taken (iso8601) False
Wafer WAFER_NAME Wafer Identifier Code False
Die Index DIE_INDEX Index of this chip on the Wafer die False
Wafer X Position WAFER_POS_X Physical X position of this chip on the wafer die (uncalibrated microns) False
Wafer Y Position WAFER_POS_Y Physical Y position of this chip on the wafer die (uncalibrated microns) False
Pass Power Probing Test PASS_POWER If chip passed power tests during probing False
Pass Digital Probing Test PASS_DIGITAL If chip passed digital readout tests during probing False
Pass Analog Probing Test PASS_ANALOG If chip passed analog tests during probing False
Optimal LDO Setting OPTIMAL_LDO_SETTING Chip LDO setting for optimal voltage (1.2V), as seen during probing False
Optimal LDO Voltage OPTIMAL_LDO_FMC_VDDREG Voltage of optimal LDO setting, as seen during probing False
Optimal LDO Raw Input Voltage OPTIMAL_LDO_FMC_VDDRAW Raw voltage when deriving optimal LDO setting, as seen during probing False
Optimal Gain Setting OPTIMAL_GAIN_SETTING Chip setting to get optimal gain (1 count per mV), as seen during probing False
Optimal Gain Slope OPTIMAL_GAIN_SLOPE Measured slope (counts/V) of optimal gain setting, as seen during probing False
Optimal Gain Intercept OPTIMAL_GAIN_INTERCEPT Measured intercept (counts) of optimal gain setting, as seen during probing False
Optimal Gain: Reduced Chi2 OPTIMAL_GAIN_REDUCEDCHI2 Reduced Chi2 of linear fit for optimal LDO setting, as seen during probing False
Max LDO Setting MAX_LDO_SETTING Highest LDO setting at which maximum (plateau) LDO value is reached False
Maximum Bandgap Voltage MAX_LDO_FMC_VDDREG Maximum bandgap value (at LDO setting of zero) False
Startup Voltage STARTUP_VOLTAGE FMC regulated voltage on startup False

Flags

No flags found for object

Stages

Table

name code order alternative initial final
On Wafer ON_WAFER 0 False True False
Probed PROBED 1 True False False
Failed Visual Inspection FAILED_VI 2 True False False
Category B CATEGORY_B 3 True False False
Category T CATEGORY_T 4 True False False
Category X CATEGORY_X 5 True False False
On Single Chip Board ON_SCB 6 True False False
Selected for bond pulling BOND_PULLING 7 True False False
Category A CATEGORY_A 8 False False True

Mermaid Diagram

flowchart LR subgraph Production Stages subgraph "On Wafer" a1["code: ON_WAFER"] a2["tests: "] end subgraph "Probed (alternative)" b1["code: PROBED"] b2["tests: HCCProbe DCS Scan HCCProbe Register Defaults HCCProbe Digital HCCID Response HCCProbe Digital Triggering HCCProbe Digital Error Blocks HCCProbe Digital Stuck Memory HCCProbe Digital ABC Passthrough HCCProbe Digital HCC Passthrough HCCProbe LDO Scan HCCProbe Calibration Scan HCCProbe Digital External Resets HCCProbe Digital Output Idles HCCProbe Fuse ID HCCProbe Digital Triplicated Clocks HCCProbe Digital Shmoo Scan HCCProbe Startup "] end subgraph "Failed Visual Inspection (alternative)" c1["code: FAILED_VI"] c2["tests: "] end subgraph "Category B (alternative)" d1["code: CATEGORY_B"] d2["tests: "] end subgraph "Category T (alternative)" e1["code: CATEGORY_T"] e2["tests: "] end subgraph "Category X (alternative)" f1["code: CATEGORY_X"] f2["tests: "] end subgraph "On Single Chip Board (alternative)" g1["code: ON_SCB"] g2["tests: Fast TID "] end subgraph "Selected for bond pulling (alternative)" h1["code: BOND_PULLING"] h2["tests: Pull Test "] end end subgraph Final Stages subgraph "Category A" i1["code: CATEGORY_A"] i2["tests: Visual Inspection "] end end

Relatives

Parents

type: *

name code
Hybrid (Obsolete) HYBRID
Hybrid (Obsolete) HYBRID
Hybrid (Obsolete) HYBRID
HCC Gelpack HCC_GELPACK
ASIC Shipping Container ASIC_SHIPPING_CONTAINER

type: HCC130

name code
HCC Wafer HCC_WAFER
Hybrid (Obsolete) HYBRID
Hybrid (Obsolete) HYBRID
Hybrid (Obsolete) HYBRID
Hybrid (Obsolete) HYBRID

type: HCCSTAR

name code
HCC Wafer HCC_WAFER
Mixed Wafer MWAFER
Hybrid (Obsolete) HYBRID
Hybrid (Obsolete) HYBRID
Hybrid (Obsolete) HYBRID
Hybrid (Obsolete) HYBRID
Hybrid (Obsolete) HYBRID
Hybrid (Obsolete) HYBRID
Hybrid (Obsolete) HYBRID
Hybrid (Obsolete) HYBRID
Hybrid (Obsolete) HYBRID
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
UofT Star Hybrid Assembly TestClone UofT_Star_Hybrid_Assembly_TestClone

type: HCCSTARV1

name code
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
STAR Hybrid Assembly HYBRID_ASSEMBLY
UofT Star Hybrid Assembly TestClone UofT_Star_Hybrid_Assembly_TestClone
Mixed Wafer MWAFER

Children