ComponentType Structure for Module PCB¶
Tables generated from PDB componentType data-strucutre
Types¶
| name | code | existing |
|---|---|---|
| Triplet L0 Stave PCB | TRIPLET_L0_STAVE_PCB | True |
| Triplet L0 R0 PCB | TRIPLET_L0_R0_PCB | True |
| Triplet L0 R0.5 PCB | TRIPLET_L0_R0.5_PCB | True |
| Quad PCB | QUAD_PCB | True |
| Dual PCB | DUAL_PCB | True |
| Single PCB | SINGLE_PCB | True |
| Tutorial PCB | TUTORIAL_PCB | True |
Properties¶
| name | code | description | required |
|---|---|---|---|
| PCB Manufacturer | PCB_MANUFACTURER | PCB Manufacturer | True |
| PCB design version | PCB_DESIGN_VERSION | PCB design version | True |
| PCB vendor technology | PCB_VENDOR_TECHNOLOGY | PCB vendor technology | True |
| SMD population vendor | SMD_POPULATION_VENDOR | False |
Flags¶
No flags found for object
Stages¶
Table¶
| name | code | order | alternative | initial | final |
|---|---|---|---|---|---|
| Reception | PCB_RECEPTION | 1 | False | True | False |
| Population | PCB_POPULATION | 2 | False | False | False |
| Cutting | PCB_CUTTING | 3 | False | False | False |
| QA pre-thermal cycle | QA_PRE_THERMAL_CYCLE | 4 | True | False | |
| QA post-thermal cycle | QA_POST_THERMAL_CYCLE | 5 | True | False | |
| QC | PCB_QC | 6 | False | False | False |
| Test failed, needs investigation | UNHAPPY | 7 | True | True | |
| PCB Reception at module site | PCB_RECEPTION_MODULE_SITE | 9 | False | False | False |
| PCB Complete | COMPLETE | 10 | False | False | False |
| Bare module to module PCB assembly | MODULE/ASSEMBLY | 11 | False | False | False |
| Wire Bonding | MODULE/WIREBONDING | 12 | False | False | False |
| Initial Warm | MODULE/INITIAL_WARM | 13 | False | False | False |
| Initial Cold | MODULE/INITIAL_COLD | 14 | False | False | False |
| Parylene Masking | MODULE/PARYLENE_MASKING | 15 | False | False | False |
| Parylene Coating | MODULE/PARYLENE_COATING | 16 | False | False | False |
| Parylene Unmasking | MODULE/PARYLENE_UNMASKING | 17 | False | False | False |
| Post-Parylene Warm | MODULE/POST_PARYLENE_WARM | 18 | False | False | False |
| Post-Parylene Cold | MODULE/POST_PARYLENE_COLD | 19 | False | False | False |
| Wirebond Protection (alt) | MODULE/WIREBOND_PROTECTION | 20 | False | False | False |
| Thermal Cycles | MODULE/THERMAL_CYCLES | 21 | False | False | False |
| Long Term Stability Test | MODULE/LONG_TERM_STABILITY_TEST | 22 | False | False | False |
| Final Warm | MODULE/FINAL_WARM | 23 | False | False | False |
| Final Cold | MODULE/FINAL_COLD | 24 | False | False | False |
| Modules failed test, needs investigation | MODULE/UNHAPPY | 25 | True | False | False |
| Module Complete | MODULE/COMPLETE | 26 | False | False | True |
Mermaid Diagram¶
flowchart LR
subgraph Production Stages
subgraph "Reception"
a1["code: PCB_RECEPTION"]
a2["tests:
Visual Inspection
Metrology
Dowel Tolerance Check
Layer thickness measurement
"]
end
subgraph "Population"
b1["code: PCB_POPULATION"]
b2["tests:
Visual Inspection
Component Position Check
"]
end
subgraph "Cutting"
c1["code: PCB_CUTTING"]
c2["tests:
Quick visual inspection
"]
end
subgraph "QA pre-thermal cycle (alternative)"
d1["code: QA_PRE_THERMAL_CYCLE"]
d2["tests:
SLDO and precision resistors
NTC Verification
Signal Transmission
Via resistance
Wirebond pull test
Layer thickness measurement
"]
end
subgraph "QA post-thermal cycle (alternative)"
e1["code: QA_POST_THERMAL_CYCLE"]
e2["tests:
NTC Verification
Via resistance
Wirebond pull test
"]
end
subgraph "QC"
f1["code: PCB_QC"]
f2["tests:
LV and HV Test
Dowel Tolerance Check
"]
end
subgraph "PCB Reception at module site"
h1["code: PCB_RECEPTION_MODULE_SITE"]
h2["tests:
Visual Inspection
Mass
Metrology
"]
end
subgraph "PCB Complete"
i1["code: COMPLETE"]
i2["tests:
"]
end
subgraph "Bare module to module PCB assembly"
j1["code: MODULE/ASSEMBLY"]
j2["tests:
"]
end
subgraph "Wire Bonding"
k1["code: MODULE/WIREBONDING"]
k2["tests:
"]
end
subgraph "Initial Warm"
l1["code: MODULE/INITIAL_WARM"]
l2["tests:
"]
end
subgraph "Initial Cold"
m1["code: MODULE/INITIAL_COLD"]
m2["tests:
"]
end
subgraph "Parylene Masking"
n1["code: MODULE/PARYLENE_MASKING"]
n2["tests:
"]
end
subgraph "Parylene Coating"
o1["code: MODULE/PARYLENE_COATING"]
o2["tests:
"]
end
subgraph "Parylene Unmasking"
p1["code: MODULE/PARYLENE_UNMASKING"]
p2["tests:
"]
end
subgraph "Post-Parylene Warm"
q1["code: MODULE/POST_PARYLENE_WARM"]
q2["tests:
"]
end
subgraph "Post-Parylene Cold"
r1["code: MODULE/POST_PARYLENE_COLD"]
r2["tests:
"]
end
subgraph "Wirebond Protection (alt)"
s1["code: MODULE/WIREBOND_PROTECTION"]
s2["tests:
"]
end
subgraph "Thermal Cycles"
t1["code: MODULE/THERMAL_CYCLES"]
t2["tests:
"]
end
subgraph "Long Term Stability Test"
u1["code: MODULE/LONG_TERM_STABILITY_TEST"]
u2["tests:
"]
end
subgraph "Final Warm"
v1["code: MODULE/FINAL_WARM"]
v2["tests:
"]
end
subgraph "Final Cold"
w1["code: MODULE/FINAL_COLD"]
w2["tests:
"]
end
subgraph "Modules failed test, needs investigation (alternative)"
x1["code: MODULE/UNHAPPY"]
x2["tests:
"]
end
end
subgraph Final Stages
subgraph "Test failed, needs investigation (alternative)"
g1["code: UNHAPPY"]
g2["tests:
"]
end
subgraph "Module Complete"
y1["code: MODULE/COMPLETE"]
y2["tests:
"]
end
end
Relatives¶
Parents¶
type: TRIPLET_L0_STAVE_PCB
| name | code |
|---|---|
| Module | MODULE |
| Module | MODULE |
| Module | MODULE |
type: TRIPLET_L0_R0_PCB
| name | code |
|---|---|
| Module | MODULE |
| Module | MODULE |
| Module | MODULE |
type: TRIPLET_L0_R0.5_PCB
| name | code |
|---|---|
| Module | MODULE |
| Module | MODULE |
| Module | MODULE |
type: QUAD_PCB
| name | code |
|---|---|
| Module | MODULE |
| Module | MODULE |
| Module | MODULE |
| Module | MODULE |
| Module | MODULE |
| Module | MODULE |
type: DUAL_PCB
| name | code |
|---|---|
| Module | MODULE |
type: SINGLE_PCB
| name | code |
|---|---|
| Module | MODULE |
type: *
| name | code |
|---|---|
| OB Loaded Module Cell | OB_LOADED_MODULE_CELL |
type: TUTORIAL_PCB
| name | code |
|---|---|
| Module | MODULE |