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ComponentType Structure for Module

Notice

Page generated: 2023-06-01

See source code here

For updates/fixes contact: wraightATcern.ch

Tables generated from PDB componentType data-strucutre

Types

name code existing
Triplet L0 stave module TRIPLET_L0_STAVE_MODULE True
Triplet L0 Ring0 module TRIPLET_L0_RING0_MODULE True
Triplet L0 Ring0.5 module TRIPLET_L0_RING0.5_MODULE True
L1 quad module L1_QUAD_MODULE True
Outer system quad module OUTER_SYSTEM_QUAD_MODULE True
Dual chip module DUAL_CHIP_MODULE True
Digital triplet L0 stave module DIGITAL_TRIPLET_L0_STAVE_MODULE True
Digital triplet L0 ring0 module DIGITAL_TRIPLET_L0_RING0_MODULE True
Digital triplet L0 ring0.5 module DIGITAL_TRIPLET_L0_RING0.5_MODULE True
Digital quad module DIGITAL_QUAD_MODULE True
Dummy triplet L0 stave module DUMMY_TRIPLET_L0_STAVE_MODULE True
Dummy triplet L0 ring0 module DUMMY_TRIPLET_L0_RING0_MODULE True
Dummy triplet L0 ring0.5 module DUMMY_TRIPLET_L0_RING0.5_MODULE True
Dummy quad module DUMMY_QUAD_MODULE True
Digital L1 quad module DIGITAL_L1_QUAD_MODULE True
Dummy L1 quad module DUMMY_L1_QUAD_MODULE True
Single chip module SINGLE_CHIP_MODULE True
Tutorial module TUTORIAL_MODULE True

Properties

name code description required
PCB-Bare Orientation isNormal ORIENTATION Normal/Upside-down (Normal=True,Upside down=False) True
FE chip version FECHIP_VERSION True
Wirebond protection roof presence ROOF Wirebond protection roof False

Flags

No flags found for object

Stages

Table

name code order alternative initial final
Bare module to module PCB assembly MODULE/ASSEMBLY 1 False True False
Wire Bonding MODULE/WIREBONDING 2 False False False
Initial Warm MODULE/INITIAL_WARM 3 False False False
Initial Cold MODULE/INITIAL_COLD 4 False False False
Parylene Masking MODULE/PARYLENE_MASKING 5 False False False
Parylene Coating MODULE/PARYLENE_COATING 6 False False False
Parylene Unmasking MODULE/PARYLENE_UNMASKING 7 False False False
Post-Parylene Warm MODULE/POST_PARYLENE_WARM 8 False False False
Post-Parylene Cold MODULE/POST_PARYLENE_COLD 9 False False False
Wirebond Protection (alt) MODULE/WIREBOND_PROTECTION 10 False False False
Thermal Cycles MODULE/THERMAL_CYCLES 11 False False False
Long Term Stability Test MODULE/LONG_TERM_STABILITY_TEST 12 False False False
Final Warm MODULE/FINAL_WARM 13 False False False
Final Cold MODULE/FINAL_COLD 14 False False False
Reception at module loading site MODULERECEPTION 15 False False False
Module loaded LOADINGCOMPLETE 16 False False False
Modules failed test, needs investigation MODULE/UNHAPPY 17 True False False
Module Complete MODULE/COMPLETE 18 False False True

Mermaid Diagram

flowchart LR subgraph Production Stages subgraph "Bare module to module PCB assembly" a1["code: MODULE/ASSEMBLY"] a2["tests: Mass Measurement Quad Module Metrology Glue Information Module+Flex Attach Triplet Module Metrology Visual Inspection Flatness "] end subgraph "Wire Bonding" b1["code: MODULE/WIREBONDING"] b2["tests: Wirebonding Information Wirebond pull test Visual Inspection "] end subgraph "Initial Warm" c1["code: MODULE/INITIAL_WARM"] c2["tests: Electrical Test (e-test) Module Summary IV measurement "] end subgraph "Initial Cold" d1["code: MODULE/INITIAL_COLD"] d2["tests: Electrical Test (e-test) Module Summary IV measurement "] end subgraph "Parylene Masking" e1["code: MODULE/PARYLENE_MASKING"] e2["tests: Visual Inspection "] end subgraph "Parylene Coating" f1["code: MODULE/PARYLENE_COATING"] f2["tests: Parylene Properties Visual Inspection "] end subgraph "Parylene Unmasking" g1["code: MODULE/PARYLENE_UNMASKING"] g2["tests: Mass Measurement Flatness Visual Inspection IV measurement Electrical Test (e-test) Module Summary "] end subgraph "Post-Parylene Warm" h1["code: MODULE/POST_PARYLENE_WARM"] h2["tests: Electrical Test (e-test) Module Summary IV measurement "] end subgraph "Post-Parylene Cold" i1["code: MODULE/POST_PARYLENE_COLD"] i2["tests: Electrical Test (e-test) Module Summary IV measurement "] end subgraph "Wirebond Protection (alt)" j1["code: MODULE/WIREBOND_PROTECTION"] j2["tests: Electrical Test (e-test) Module Summary Wire bonding protection roof envelope Mass Measurement Visual Inspection IV measurement "] end subgraph "Thermal Cycles" k1["code: MODULE/THERMAL_CYCLES"] k2["tests: Electrical Test (e-test) Module Summary Thermal Cycling Flatness Visual Inspection IV measurement "] end subgraph "Long Term Stability Test" l1["code: MODULE/LONG_TERM_STABILITY_TEST"] l2["tests: Electrical Test (e-test) Module Summary IV measurement "] end subgraph "Final Warm" m1["code: MODULE/FINAL_WARM"] m2["tests: Electrical Test (e-test) Module Summary IV measurement "] end subgraph "Final Cold" n1["code: MODULE/FINAL_COLD"] n2["tests: Electrical Test (e-test) Module Summary IV measurement "] end subgraph "Reception at module loading site" o1["code: MODULERECEPTION"] o2["tests: "] end subgraph "Module loaded" p1["code: LOADINGCOMPLETE"] p2["tests: "] end subgraph "Modules failed test, needs investigation (alternative)" q1["code: MODULE/UNHAPPY"] q2["tests: "] end end subgraph Final Stages subgraph "Module Complete" r1["code: MODULE/COMPLETE"] r2["tests: "] end end

Relatives

Parents

type: *

name code
OB Loaded Module Cell OB_LOADED_MODULE_CELL
OB Loaded Module Cell OB_LOADED_MODULE_CELL

type: DUMMY_TRIPLET_L0_RING0_MODULE

name code
IS Loaded Local Support IS_LOADED_LOCAL_SUPPORT

type: TRIPLET_L0_STAVE_MODULE

name code
IS Loaded Local Support IS_LOADED_LOCAL_SUPPORT

type: L1_QUAD_MODULE

name code
IS Loaded Local Support IS_LOADED_LOCAL_SUPPORT
IS Loaded Local Support IS_LOADED_LOCAL_SUPPORT
IS Loaded Local Support IS_LOADED_LOCAL_SUPPORT

type: TRIPLET_L0_RING0.5_MODULE

name code
IS Loaded Local Support IS_LOADED_LOCAL_SUPPORT

Children

type: TRIPLET_L0_STAVE_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: TRIPLET_L0_RING0_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: TRIPLET_L0_RING0.5_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: L1_QUAD_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: OUTER_SYSTEM_QUAD_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: DUAL_CHIP_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: DIGITAL_TRIPLET_L0_STAVE_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: DIGITAL_TRIPLET_L0_RING0_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: DIGITAL_TRIPLET_L0_RING0.5_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: DIGITAL_QUAD_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: DUMMY_TRIPLET_L0_STAVE_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: DUMMY_TRIPLET_L0_RING0_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: DUMMY_TRIPLET_L0_RING0.5_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: DUMMY_QUAD_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: DIGITAL_L1_QUAD_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: DUMMY_L1_QUAD_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB

type: SINGLE_CHIP_MODULE

name code
Bare Module BARE_MODULE
Module PCB PCB
Module carrier MODULE_CARRIER

type: TUTORIAL_MODULE

name code
Module carrier MODULE_CARRIER
Bare Module BARE_MODULE
Module PCB PCB